The present invention relates to an integrated semiconductor chip having one or more leads to be connected to one or more external terminals of a supply voltage.
A semiconductor module whose housing contains a silicon chip having on-chip terminals to one or more integrated circuits situated on the silicon chip is usually provided with leads from one or more of such internal terminals to one or more terminals which are situated outside the chip area. Such terminals may be, for example, terminals for external voltage supplies or connections to other assemblies that are situated for example on a circuit board outside the module. In many embodiments, the leads are bent at a right angle at the locations at which they are contact-connected to the external terminals (for example contacts on the circuit board). In order to minimize the power loss in the leads of the chip, the leads are generally configured to have the lowest possible impedance.
Ever higher data rates for integrated semiconductor chips are the cause of ever higher clock rates at which the chip is operated. During each clock cycle, a certain amount of energy is consumed on the chip, this causing current pulses on the leads of the voltage supply, which become correspondingly faster and steeper at higher clock rates. The leads from the integrated circuits of a chip to the external supply potentials of a supply voltage have lead inductances that, together with capacitances on the chip, form an oscillatory system. As a result of faster and steeper current pulses on the leads, the voltage drop across the inductances and capacitances also rises, oscillations thereby being excited which can ultimately result in undesirable resonance oscillations. Thus, the associated influence on the internal voltage supply can no longer be disregarded. Steep current pulses can consequently result in the excitation of potential fluctuations, which oscillate periodically and can ultimately result in resonances at the internal terminals of the respective lead of the chip, and they can impair the functioning of the chip. Since different functional groups of the chip, such as logic circuits or output drivers, are connected to the supply voltage, potential fluctuations at the internal supply voltage of one functional group can also influence the voltage supply of the respective other functional groups. Depending on the sensitivity of the respective circuits toward irregularities in the supply voltage, the functioning of the chip may be jeopardized in this case.
Attempts have previously been made to configure semiconductor chips such that potential fluctuations at the internal voltage supply do not influence the operation of the semiconductor chip. Therefore, the switching speed of a chip is only allowed to reach a level where voltage fluctuations that are still just acceptable are caused. However, this results in losses in the data transmission speed of a chip. In order to adapt the maximum permissible data transmission rate of the semiconductor chip optimally to an application, it is necessary, accordingly, to specify the ambient conditions of the chip (for example capacitances, inductances), depending on the application. This is scarcely possible, however, on account of the large number of influencing variables in a digital circuit. Moreover, such a measure has the effect of restriction to a defined area of application of the semiconductor chip. Another possibility is to attenuate potential fluctuations at an internal terminal of a lead by providing an attenuation resistor having a defined resistance on the chip. Such a resistor does not undertake any further tasks apart from this in an integrated circuit. Consequently, additional valuable area on the chip is necessary in order to accommodate such a resistor.
It is accordingly an object of the invention to provide an integrated semiconductor chip having leads to one or more external terminals which overcomes the above-mentioned disadvantages of the prior art devices of this general type, which attenuates potential fluctuations at an internal terminal of a lead of an integrated semiconductor chip, the fluctuations being excited by current pulses on the lead, in such a way that the internal voltage supply is stabilized even at high clock rates and the functioning of the chip remains ensured, without an additionally necessary chip area intended for this purpose being required.
With the foregoing and other objects in view there is provided, in accordance with the invention, an integrated semiconductor chip, including an internal terminal and a lead having a first end connected to the internal terminal, a second end to be connected to an external terminal of a supply voltage, and a given total length, the lead further having a resistance large enough for it to sufficiently attenuate potential fluctuations at the internal terminal, the potential fluctuations being excited by current pulses on the lead, but the resistance being small enough to cause only a predetermined maximum permissible voltage drop for a maximum current on the lead, the lead also having a cross section reduced within a delimited section effecting the resistance by virtue of the fact that the cross section of the lead is reduced within the delimited section and the delimited section having a length being small relative to the given total length of the lead.
In accordance with an added feature of the invention, the cross section reduced within the delimited section is a notch formed in the lead.
In accordance with another feature of the invention, a size ratio between the length of the delimited section having the notch and the given total length of the lead is 1:1000.
In accordance with a concomitant feature of the invention, the notch in the lead is effected by one of etching and by cutting the lead with a laser.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an integrated semiconductor chip having leads to one or more external terminals, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.